FPGA, EDA Tools, and VLSI Design
| Session 1 | ||||
| Paper ID | Paper Title | |||
| 5 | Hardware Acceleration of Activation Functions using Piecewise-Legendre Polynomial Approximation Technique | |||
| 96 | HYDRA: Hybrid Data Multiplexing and Run-time Layer Configurable DNN Accelerator | |||
| 152 | Comprehensive Noise Modeling and Analysis for SRAM, RRAM, and MRAM for Analog In-Memory Computing | |||
| 115 | Design and Image Encryption Implementation of High Performance and Resource-Efficient AES-128 Encryption Architecture | |||
| 155 | Hardware Implementation of an Efficient Two Error Correcting BCH Code Decoder | |||
| 157 | A novel low power modified folded cascode OTA for brain machine interface application | |||